This application claims the priority benefit of Taiwan application ser. no. 89113381, filed Jul. 6, 2000.
1. Field of the Invention
The present invention relates to a method of manufacturing of a bit line. More particularly, the present invention relates to a method of manufacturing which uses a graded buried junction to suppress the punch-through of a memory cell bit line (BL) and the leakage increase of a mask ROM BL.
2. Description of the Related Art
Currently, ROM designs have been restricted by the technology of semiconductor manufacturing, and the reduced measurements of the ROM device requires further improvements in manufacturing techniques. The ROM in the related art is made of an array of field effect transistors (FET). Each memory cell includes a single FET device and each FET device provides one of the two set values as a special transistor characteristic.
The generally used mask ROM utilizes a channel transistor as a memory cell, and selectively implant ions into the specified channel regions in the programming stage. By changing the threshold voltage, it controls the on/off function of the memory cell. The structure of the mask ROM is a polysilicon word line (WL) which intersects with the BL almost perpendicularly. The channel of the memory cell forms on the covered lower portion of the WL and the region between the BLs. This selective transistor with special characteristics utilizes the difference of the transistor threshold voltage. When there are implant impurities in the channel region of the transistor, it causes the transistor to have a relatively low threshold voltage, then a voltage Vcc is applied to the gate and causes the channel to open. If the channel region of the transistor does not have implant impurities, then the transistor has a relatively high threshold voltage, which also means that the channel is not opened by the voltage Vcc that has been applied to the gate. Therefore, the binary data selectively implants impurities into the channel region of the transistor to store into the ROM. When the channel region of the transistor implants impurities, it is stored as logic value xe2x80x980xe2x80x99; as the channel region does not have implant impurities, it is stored as logic value xe2x80x981xe2x80x99.
Presently, the implementation of memory transistors is limited in the technique of the design rules, moreover consideration of the device design is also limited to the degree of stored materials that the ROM in the related art is capable of increasing. For example, the ROM in the related art, uses buried N+ type lines (itself or also with the source/drain and BL) to connect to a source/drain diffusion region of a row of transistors. These connecting N+ lines become decreasingly small as the design rules decrease. After the integration rate of the device becomes increasingly high, since this type of buried BL has no way of effectively lowering resistance, thus, it prevents the ROM from operating at an even higher speed. The most important reason is that in the doping of the high concentration of the N+ type ion, resistance is only lowered to about 70 to 80 ohm-cm. If in order to lower the resistance, the quantity of ion implantation continues to increase, a punch-through of the memory cell BL results. Furthermore, if the doping concentration of the N+ type ion is increased, the junction forms a leakage increase. Hence, this type of mask ROM buried BL manufacturing, is only suitable for use on procedures from about 0.45xcexc to 0.5xcexc. If the integration rate of the mask ROM increases, then the related art procedure is not suitable, and requires the development of a new procedure.
Accordingly, the present invention provides a method of manufacturing ROM BL. The method of ion implantation is no longer utilized to form a buried mask ROM BL, but rather, a sacrificial silicon oxide layer is formed on the active region delimited by a field oxide (FOX) layer. Numerous parallel openings are formed on the sacrificial silicon oxide layer. A polysilicon layer which includes the several parallel openings, is formed upon the sacrificial silicon oxide layer. The polysilicon layer which is formed on the sacrificial silicon oxide layer performs ion implantation. For example, the thickness of the polysilicon layer formed by the low pressure chemical vapor deposition (LPCVD) is from about 1000 xc3x85 to 3000 xc3x85, and the concentration of the implanted ions is from about 1014 to 1017 atoms/cm2. The ion subsequently undergoes a thermal procedure via the sacrificial silicon oxide layer drive-in opening of the silicon substrate, and forms an ion concentration into a graded buried junction. The nearer the ions are to the openings of the sacrificial silicon oxide layer, the higher the concentration, and conversely, the further away the ions are, the lower the concentration. Moreover, the polysilicon layer is etched back and the sacrificial silicon oxide layer is removed to form the BL. A gate oxide layer, a polysilicon layer, a silicide layer and a photoresist are sequentially formed upon the polysilicon layer and the substrate. The photoresist is patterned and then selectively etchbacks the exposed silicide layer and the polysilicon layer, and also selectively etchbacks the gate oxide layer. The photoresist layer is removed to form a gate, and is used as a WL.
According to the procedure provided in the present invention, a doped polysilicon conductive wire formed on the substrate, and an ion doping region located in the lower portion of the doped polysilicon conductive wire, form a BL together. Since the conductive wire is located on the surface of the substrate, there is no need to worry that high concentration doping causes the BL to be punched through. Therefore, it performs high concentration doping of the doped polysilicon conductive wire to lower BL resistance. Moreover, by using a thermal flow procedure to dope polysilicide BL ions and drive them into the substrate to form an arched diffusion, the ions concentrate into a graded buried junction. When the high ion concentration of the shallow junction lowers the junction resistance, and the low ion concentration of the deep junction reduces leakage, the side junction low ion concentration prevents a punch-through from occurring.
As embodied and broadly described herein, one of the objectives of the present invention is to provide a method of manufacturing a mask ROM BL. The present manufacturing procedure uses a doped polysilicon layer of the openings of a sacrificial silicon oxide layer and the buried junction of the lower portion to form a BL.
Another objective of the present invention is to provide a method of manufacturing a mask ROM BL. The present manufacturing procedure utilizes a sacrificial silicon oxide layer as a mask. Via a thermal flow procedure through the openings of the sacrificial silicon oxide layer, the doped ions in the polysilicon layer are driven into the substrate and form a buried junction.
Yet another objective of the present invention is to provide a method of manufacturing a mask ROM BL. The present manufacturing procedure is that a buried junction of a graded ion concentration with an arched diffusion is formed on the lower portion of a doped polysilicon BL. The closer it is to the center of the arc, the higher the ion concentration; conversely, the further away it is from the center of the arc, the lower the ion concentration.
A another objective of the present invention is to provide a method of manufacturing a mask ROM BL. The present manufacturing procedure lowers the BL resistance and utilizes the junction of the graded ion concentration arched diffusion in order to prevent the a punch-through of the BL from happening. Moreover, the low concentration of ion doping on the edge of the arc reduces the incidence of leakage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.